Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. Miniaturization in general allows increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost.
Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, FETs, capacitors, etc. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates. The present invention is directed to such micro-sized FET devices.
Basically a FET is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate. More than one gate (multi-gate) can be used to more effectively control the channel. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (i.e., the distance between the source and drain). Multi-gate FETs are considered to be promising candidates to scale CMOS FET technology down to the sub-22 nm regime. However, such small dimensions necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current and, of particular relevance herein, the parasitic resistance that is present in a multi-gate FET.
The size of FETs has been successfully reduced through the use of one or more fin-shaped channels. A FET employing such a channel structure can be referred to as a FinFET. Previously, complementary metal-oxide semiconductor (CMOS) devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
One challenge in fabricating multi-gate FETs is the high parasitic resistance due to the ultra-thin body channel, which can significantly degrade the drive current. The parasitic resistance is believed to be due mainly to sheet resistance under a spacer layer, and contact resistance in the source and drain (S/D) regions.
What is needed is a technique to reduce the parasitic resistance in a FET device such as a multi-gate FET device.